1. Field of the Invention
This invention relates to integrated circuit inspection techniques. Still more particularly, this invention relates to the use of scanning electron microscopes for investigating the properties of dynamically operated integrated circuits by utilizing identifiable contrast differences corresponding to phase conditions on the IC.
2. Description of the Prior Art
The use of scanning electron microscopes to investigate variations of potential on the surface of semiconductor integrated circuits was first reported in the late 1950's. Since that time the technique has been widely employed and developed. This technique offers important advantages over alternative methods such as mechanical probing. With reduced geometries and higher densities in the latest semiconductor integrated circuit devices, the physical dimensions of the individual channels on the devices will soon exceed the limits of optical resolution. Indeed, SEM troubleshooting methods may emerge as the only viable technique with which to analyze and inspect such devices.
The most useful SEM methods utilize voltage contrast for IC analysis and fault detection. The phenomenon of voltage contrast in scanning electron microscopy arises due to the fact that the potential of any given location of a specimen being bombarded by an electron beam plays a significant role in the number of electrons being collected by the electron detector within the SEM. A positive specimen bias results in a reduction of the number of electrons collected, while a negative bias has the opposite effect. In general, more negatively biased areas produce a stronger signal than do the more positively biased areas.
One voltage contrast technique utilizes chopping of the incident electron beam probe at a sufficiently high frequency such that several cycles occur while the probe is moving from one picture point to the next. The pulses of current arriving at the detector are amplified and the output is passed to two parallel electric gates, A and B, operated in such a way that alternate pulses travel through separate channels. External bias is applied to the specimen by a square wave voltage whose frequency is half that of the chopping frequency, and whose phase is adjusted so that the signals in channel A come from a biased specimen, while those in channel B originate from an unbiased specimen. The outputs from the two channels are passed through a differential amplifier and the resulting difference signal is lead to the display monitor of the SEM.
Other voltage contrast techniques employ continuous electron beam probes, but each of these methods contain important limitations which restrict their application and effectiveness. There are no prior art voltage contrast SEM techniques known at the present time with continuous electron beam probes which can display both logic state information as well as timing information regarding signal propagation delays expressed as voltage contrasts, differences corresponding to phase conditions on the integrated circuit specimen under test.